By Ravi Srinivasan
Integrated System Design
Posted 12/05/01, 03:43:53 PM EDT

Today's system-on-chip development requires multiple design teams, often located in extended geographies with different design cultures. Each team brings the specialized design discipline required to meet the SoC project goals. Being able to plan and execute to a predictable project schedule with such a challenging development process can be the difference between success and failure in the market.

Project managers struggle to answer a common question: How can development teams forecast the design to be completed in five weeks (tapeout-ready) and yet regularly miss the schedule by an entire quarter?

Failure to meet schedule often results in a blame game, with finger pointing within and between different groups. This breakdown in teamwork has a strong negative impact on morale. From a management perspective, each schedule delay carries a serious impact on profitability. This article covers the problems design teams and managers face in developing and completing an SoC design on a predictable schedule.

Today, nearly all project planning begins with a bottom-up project schedule that is based on a previous design effort. Managers then apply to this schedule a top-down estimate to meet the business objectives and employ program-management best practices to execute it. This planning method develops what seems to be a reasonable schedule for the design teams to meet. What happens in the development process is another story. Technical managers often stumble into critical bottlenecks at many stages of the process. Some of the more common bottlenecks occurring in the design, verification, and integration of the chip are depicted in Figure 1a. The result is a late and, arguably worse, an unpredictable tapeout as depicted in Figure 1b.

Design complexity increases with every design cycle; new tools and methods are required to address these challenges. Therefore, design teams require increased specialization and expertise in multiple areas, such as design planning, signal integrity and IP-based chip assembly on almost every project. Unfortunately, designers often tackle these bottlenecks as they encounter them. They are unable to avoid them and their resulting schedule slips.

From the design engineer's perspective, it is natural to find fault with top-down planning. But in reality, the top-down management judgment is not the root of the problem. Business managers deal with multiple conflicting factors. To realize the company's business goals, they must trade off time-to-market and quality of results, maximizing performance and minimizing risks, containing costs and getting it done on time at all costs. The root cause actually stems from underestimating the technical challenges (design bottlenecks) and failing to develop plans to address or avoid them.

Two real-world scenarios illustrate the technical, project and personnel challenges teams face in creating complex SoC designs. The following is a description of those scenarios. Later, an approach and practical suggestions for resolving the challenges are presented. The names of the companies are fictional.

In the first scenario, Globalcom, a large semiconductor company, has a design team of more than 35 engineers chartered to develop a 250-Mhz wireless design platform targeted to a 0.13-micron internal process. The platform acts as the baseline design that is deployed to multiple design centers for rapid development of derivative designs. The design platform includes application-specific logic, several standards-based peripherals and three major subsystems (microprocessors, DSP and memory). About 70 percent of the design's gate count is being reused from a previous-generation design.

The full-chip design is integrated from 12 different remote design centers on three continents: North America, Europe and Asia. Some of the greater challenges faced by the design teams include predicting timing performance prior to tapeout, deploying a consistent integration environment in the different design centers and migrating the design teams to a hierarchical design methodology for integrating larger SoC designs.

Each module design team is working with independent timing constraints from a previous design, and feverishly closing timing on the individual modules. There are at least 15 engineers on weekly conference calls in multiple early morning/late night time zones to discuss the status of the design modules, highlight technical obstacles and plan activities for the next week. However, the majority of the time spent on these conference calls is providing status updates-too little time is spent on problem-solving.

Managing Integration
Globalcom's project lead manages the physical integration team. In the first few weeks of the integration phase of the schedule, the project lead must sort out multiple versions of the block design input from the 12 remote design centers. The physical integration (layout) team is focused on block-finishing eight of the 12 modules while the project lead is completing a chip-level route.

The project lead requests that the module design teams complete the register-transfer level (RTL) design and hand off the netlist/placed-gates netlist to the integration team. The subsequent design releases miss the schedule and are delivered in different formats (hard block, netlist and placed-gates netlist) with varying degrees of maturity (unconstrained pins, missing pins) and functionality (missing RAM instantiations, RTL rewrite of state machines).

Because of the delays in the design of the modules, the project lead must deliver the integrated GDSII to tapeout in less than eight weeks. All the project pressure then shifts to the back end (layout), to meet the original product ship date. Before discussing an approach that resolves these challenges, let's look at another common scenario, this time with Fablesscom-a small, geographically dispersed, fabless company.

In this scenario, Fablesscom's design team is chartered to develop a 300-Mhz game console design targeted to a 0.18-micron external foundry process. About half of the design's gate count is dedicated to IP licensed from a variety of external sources, including the design libraries. A group of 30 engineers, spread across three cities (two remote design centers and an integration team) are responsible for developing the remaining portion of the design. The back-end (layout) activities are outsourced to an independent design service provider.

The two remote design centers are focused on implementing the subsystems, integrating the third-party IP blocks and verifying the final subsystems to meet the block-level goals. The project lead and a small physical integration team of three engineers are burdened with managing the interface with third-party IP vendors, tackling IP-related issues, resolving block-finishing issues and integrating the module-level designs from the two design centers to meet chip-level area and timing goals.

With just 10 weeks left in the original schedule, Fablesscom must resolve the inconsistencies in handoff, and prepare the design for tapeout.

Consistent Integration
From our analysis of these two scenarios, the common challenges design teams face indicate a need for a consistent integration environment to facilitate communication among remote design teams, a focal point of contact to resolve all critical bottlenecks and a chip-level integration plan that leads to predictable timing closure.

To make the most of the development effort, a structured approach to managing the remote design teams needs to be employed. The teams can accomplish their respective project goals by introducing the following three structured approaches:

1. Establish an early chip-level analysis framework for consistent integration (includes floor plan, formal verification and static-timing analysis) and communicate relevant information via the Web.

2. Create a successive build methodology for predictable timing closure (RTL/placed-gates netlist drop at least once every two weeks).

3. Make chip integration lead responsible not just for physical integration but for logical, too.

By employing this approach, the chip integration lead can focus all of the implementation resources on relevant bottlenecks and facilitate communication across different design teams. To be effective, design changes must be simple to record, track and proliferate to all designers. Publishing the chip-level analysis results on the Web is an effective way to solicit project-specific feedback from the remote teams.

For Globalcom, the result of implementing this structured approach was that within six weeks, the chip-level design began to converge and the project manager was able to communicate with confidence a predictable schedule to tapeout.

An important aspect of the structured integration approach is to be able to predict timing closure and scheduled completion of the full chip design. A "successive build" is a construct-by-correction methodology that incorporates design changes into each release, executes a planned set of integration tasks and reviews the full-chip results for a given release. The approach provides deterministic progress to the chip development effort.

Using this approach in managing design teams introduces predictability into the development process. So, how does the chip design progress through this process? The approach works by having the company deploy a consistent integration environment to all the remote design centers. Globalcom's integration team, for example, was able to process RTL/placed-gates input, once every two weeks. The result: Globalcom was eight weeks from tapeout from the final release of the RTL design and it taped out the design in exactly eight weeks.

This successive-build methodology introduces the desired predictability to the project schedule and guides the implementation process through all of the planned integration activities without impacting the overall project schedule.

A chip integration lead plays a critical role in the project team. This person is ultimately responsible for functionality, performance and integration of the full chip. The integration activities include design planning, chip and block finishing and full-chip sign-off (static, formal, deep-submicron) analysis prior to tapeout.

By using a chip-level analysis framework and deploying a successive-build methodology, Fablesscom's chip integration lead was able to ensure logical and physical integration of the design.

With the expanded role, the chip integration lead could now identify the critical block, adopt new methodologies to optimize it and eliminate lengthy and unproductive iterations through the back end (detailed layout).

Creating a means for improved communication on relevant data is a necessity for schedule predictability.

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Practice manager Ravi Srinivasan is responsible for all consulting service offerings from Synopsys Professional Services (Mountain View, Calif.). He has more than 12 years of industry experience and an MBA from Purdue University and an MSEE from Southern Methodist University.

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